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Adder/Subtractor
Algorithmic State Machine (ASM)
AND gate
Arithmetic Logic Unit (ALU)
Behavioural model
Boolean algebra
Carry select adder
Combinational logic
Comparator
Control unit
Counter
CPU design example (CISC)
CPU design example (RISC, basic)
D flip-flop (edge-triggered)
D latch
Dataflow model
Datapath
Decoder
Demultiplexer
De Morgan's law
Encoder
Flip-flop input equation
Full adder
Function unit
Half adder
Hardwired nonprogrammable control unit design example (greatest common divisor)
Hardwired programmable control unit design example (single cycle computer)
Instruction Set Architecture (ISA)
JK flip-flop (edge-triggered)
JK flip-flop (master-slave)
Karnaugh map
Literal
Maxterm
Mealy model
Microprogrammed nonprogrammable control unit design example (greatest common divisor)
Microprogrammed programmable control unit design example (multiple cycle computer)
Microprogramming
Minterm
Moore model
Multiplexer
Multiplier (simple)
NAND gate
NOR gate
NOT gate
OR gate
Product of sums
Propagation delay
RAM
Register (parallel load)
Register file
Register transfer level (RTL)
Ripple carry adder
ROM
Sequential logic
Sequential logic design example (traffic lights)
Shift register (bidirectional)
Shifter
Shifter (barrel)
SR flip-flop (master slave)
SR latch (gated)
SR latch (ungated)
State diagram
State table
Structural model
Sum of products
Truth table
Two's complement (2's complement)
XNOR gate
XOR gate
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