JK Flip-Flop (edge-triggered)

A JK flip-flop is used in clocked sequential logic circuits to store one bit of data. It is almost identical in function to a SR flip-flop, the only difference being the elimination of the undefined state where both S and R are 1. In the case of a JK flip-flop, when the equivalent inputs are both 1, the outputs toggle.

The type of JK flip-flop described here is an edge-triggered JK flip-flop. It is built from two gated latches: one a master gated D latch, and the other a slave gated SR latch. This is a modified edge-triggered D flip-flop — the flip-flop's outputs are fed back and combined with the inputs. The master takes the flip-flop's inputs: J (set), K (reset), and C (clock). The clock input is inverted and fed into the D latch's gate input. The slave takes the master's outputs as inputs (Q to S and Qn to R), and the complement of the master's clock input. The slave's outputs are the flip-flop's outputs. This difference in clock inputs between the two latches disconnects them and eliminates the transparency between the flip-flop's inputs and outputs.

The schematic below shows a positive edge triggered JK flip-flop. The two inputs J and K are used to set and reset the data respectively. They can also be used to toggle the data. The clock input C is used to control both the master and slave latches making sure only one of the latches can set its data at any given time. When C has the value 0, the master latch can set its data and the slave latch cannot. When C has the value 1, the slave can set its data and the master cannot. When C transitions from 0 to 1 the master has its outputs set which reflect the flip-flop's inputs when the transition occurred. The outputs Q and Qn are the flip-flop's stored data and the complement of the flip-flop's stored data respectively.

The schematic symbol for a 7476 edge-triggered JK flip-flop is shown below. This chip has inputs to asynchronously set and reset the flip-flop's data.


The following function table shows the operation of a JK flip-flop. The column header Q(t+1) means "the value of Q at the start of the next clock period", similarly for Qn(t+1).

J K Q(t+1) Qn(t+1) Meaning


Below is the Verilog code for a positive edge-triggered JK flip-flop. An active low reset input has been added to asynchronously clear the flip-flop. The code for the gated D and SR latches is also shown for completeness.

module jk_flip_flop_edge_triggered(Q, Qn, C, J, K, RESETn);
   output Q;
   output Qn;
   input  C;
   input  J;
   input  K;
   input  RESETn;

   wire   Kn;   // The complement of the K input.
   wire   D;   
   wire   D1;   // Data input to the D latch.   
   wire   Cn;   // Control input to the D latch.
   wire   Cnn;  // Control input to the SR latch.
   wire   DQ;   // Output from the D latch, inputs to the gated SR latch (S).
   wire   DQn;  // Output from the D latch, inputs to the gated SR latch (R).

   assign D1 = !RESETn ? 0 : D;  // Upon reset force D1 = 0

   not(Kn, K);   
   and(J1, J, Qn);
   and(K1, Kn, Q);   
   or(D, J1, K1);   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D1);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule // jk_flip_flop_edge_triggered

module d_latch(Q, Qn, G, D);
   output Q;
   output Qn;
   input  G;   
   input  D;

   wire   Dn; 
   wire   D1;
   wire   Dn1;

   not(Dn, D);   
   and(D1, G, D);
   and(Dn1, G, Dn);   
   nor(Qn, D1, Q);
   nor(Q, Dn1, Qn);
endmodule // d_latch

module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;

   wire   S1;
   wire   R1;
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule // sr_latch_gated

A simulation with test inputs gave the following wave form:


Kleitz, W. Digital Microprocessor Fundamentals. 3rd Edition. Prentice Hall, 2000.
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.