SR Latch (gated)
A SR latch is used to store one bit of data. It is an example of a sequential logic circuit. The type of SR latch described here is a gated SR latch which is synchronous, that is to say, the data is stored as soon as the data input is changed and a control input is given. These differ from the ungated type which are asynchronous, that is to say, the data is stored as soon as the data is changed.
The schematic below shows a gated SR latch.
The two inputs S and R are used to set and reset the data respectively.
The input G is used to control the entire latch as no changes can be made until it has the value 1.
The outputs Q and Qn are the stored data and the complement of the stored data respectively.
Example
The following function table shows the operation of a gated SR latch.
G |
S |
R |
Q |
Qn |
Meaning |
|---|---|---|---|---|---|
0 | 0 | 0 | Q | Qn | Hold |
0 | 0 | 1 | Q | Qn | Hold |
0 | 1 | 0 | Q | Qn | Hold |
0 | 1 | 1 | Q | Qn | Hold |
1 | 0 | 0 | Q | Qn | Hold |
1 | 0 | 1 | 0 | 1 | Reset |
1 | 1 | 0 | 1 | 0 | Set |
1 | 1 | 1 | 0 | 0 | Undefined |
Verilog
Below is the Verilog code for a structural model of a gated SR latch.
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule
A simulation with test inputs gave the following wave form:
References
Kleitz, W. Digital Microprocessor Fundamentals. 3rd Edition. Prentice Hall, 2000.
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.