A structural model is a description of a circuit at the abstraction level of logic gates. This type of model could be seen as a textual representation of a schematic. Modelling at such a low-level is to be contrasted with dataflow modelling and behavioural modelling which are done at a higher level of abstraction.
Consider a half adder which adds bits
B giving the sum
S and carry
The truth table below gives the specification:
The simplified equations for the half adder are:
S = A xor B
C = A and B
In schematic form this is:
Below is a Verilog structural model which shows just how closely a schematic and structural model match each other.
In the code, the first argument to
and is the gate output, the other arguments are
module half_adder(S, C, A, B); output S; output C; input A; input B; xor(S, A, B); and(C, A, B); endmodule
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.
Kleitz, W. Digital Microprocessor Fundamentals. 3rd Edition. Prentice Hall, 2000.
Copyright © 2014 Barry Watson. All rights reserved.