A behavioural model is a description of a circuit in terms of high-level logic and arithmetic operations and assignments. This is sometimes known as the register transfer level. The designer working at this level will model in terms of what the circuit will do as opposed to using the lower-level logic gates which describe how the circuit can be implemented.

Consider a half adder which adds bits `A`

and `B`

giving the sum `S`

and carry `C`

.
The truth table below gives the specification:

` A ` | ` B ` | ` S ` | ` C ` |
---|---|---|---|

`0` | `0` | `0` | `0` |

`0` | `1` | `1` | `0` |

`1` | `0` | `1` | `0` |

`1` | `1` | `0` | `1` |

The simplified equations for the half adder are:

`S = A xor B`

`C = A and B`

In schematic form this is:

The code below gives a Verilog behavioural model for a half adder.
Here there are no logic gates as you would find in a structural model.
The behaviour of the gate is given by the arithmetic expression for addition (`+`

), along with
the concatenation (`{ }`

), and continuous assignment (`assign`

).

` ````
module half_adder(S, C, A, B);
output S;
output C;
input A;
input B;
assign {C, S} = A + B;
endmodule
```

Mano, M. Morris, and Kime, Charles R. *Logic and Computer Design Fundamentals. 2nd Edition.* Prentice Hall, 2000.

Kleitz, W. *Digital Microprocessor Fundamentals. 3rd Edition.* Prentice Hall, 2000.

Copyright © 2014 Barry Watson. All rights reserved.