The schematic below shows a D latch.
D is the data to be stored.
G is used to control the storing.
Qn are the stored data and the complement of the stored data respectively.
The following function table shows the operation of a D latch.
Below is the Verilog code for a structural model of a D latch.
module d_latch(Q, Qn, G, D); output Q; output Qn; input G; input D; wire Dn; wire D1; wire Dn1; not(Dn, D); and(D1, G, D); and(Dn1, G, Dn); nor(Qn, D1, Q); nor(Q, Dn1, Qn); endmodule
A simulation with test inputs gave the following wave form:
Kleitz, W. Digital Microprocessor Fundamentals. 3rd Edition. Prentice Hall, 2000.
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.
Copyright © 2014 Barry Watson. All rights reserved.