A NOT gate is a fundamental binary logic gate with one input and one output. The output is the inverse, a.k.a. complement, of the input.

The following truth table gives the specification for a NOT gate with output `X`

:

` A ` | ` X ` |
---|---|

`0` | `1` |

`1` | `0` |

The schematic form of the NOT gate is:

Below is a Verilog structural model for the NOT gate.
In the code, the first argument to `not`

is the gate output, the other argument is the input.

` ````
module not_gate(X, A);
output X;
input A;
not(X, A);
endmodule
```

Mano, M. Morris, and Kime, Charles R. *Logic and Computer Design Fundamentals. 2nd Edition.* Prentice Hall, 2000.

Kleitz, W. *Digital Microprocessor Fundamentals. 3rd Edition.* Prentice Hall, 2000.

Copyright © 2014 Barry Watson. All rights reserved.