A half adder is a fundamental circuit in binary arithmetic which adds bits
S and carry
The following truth table gives the specification:
The simplified equations for the half adder are:
S = A xor B
C = A and B
In schematic form this is:
Below is a Verilog structural model for the half adder.
In the code, the first argument to
and is the gate output, the other arguments are
module half_adder(S, C, A, B); output S; output C; input A; input B; xor(S, A, B); and(C, A, B); endmodule
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.
Kleitz, W. Digital Microprocessor Fundamentals. 3rd Edition. Prentice Hall, 2000.
Copyright © 2014 Barry Watson. All rights reserved.