Register Transfer Level (RTL)

The register transfer level (RTL) is a description of a sequential logic circuit in terms of registers, arithmetic operations upon them, and the transferal of information between them.

Example

Below is Verilog code for a binary code counter. It is an example of RTL design. In this simple example there is only one register: count.

	
module counter(count, CLK, RESETn);
   input CLK;
   input RESETn;
   output [31:0] count;
   
   reg [31:0] count;

   always @(posedge CLK, negedge RESETn)
     begin
	if(!RESETn)
	  begin
	     count <= 0;	     
	  end
	else
	  begin
	     count <= count + 1;
	  end
     end
endmodule
	
      

The following waveform was generated when the counter was given a clock input:

References

Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.