The Instruction Set Architecture (ISA) is the interface between the processor and the programmer, i.e. the parts of the processor the programmer can see and use. The ISA usually comprises a list of processor instructions, the addressing modes these instructions can use, exception handling details, and other processor control details.
There are three main architecture types: stack architecture, accumulator architecture, and general purpose register architecture. The differences between the three mainly shows itself in how many explicit operands ALU instructions take.
The stack architecture sees ALU instructions pop their operands from a stack and push their results back onto the same stack. In this case the ALU instructions take no explicit operands.
An accumulator architecture sees ALU instructions take one explicit operand. These instructions work with an implicit register called an accumulator which is combined with the explicit operand. A typical operation might add the explicit operand to the contents of the accumulator then load the result into the accumulator.
The general purpose register architecture takes two or three explicit operands for each ALU instruction. An instance of such an architecture would have several registers which could be addressed by the ALU instructions and used as sources or destinations of the ALU operation.
Instructions are used to move data from one location (register or memory address) to another, to manipulate data (e.g. ALU operations), to send and receive data from I/O circuits, and to control processor operation (e.g. conditional jumps, disable interrupts, etc.).
This class of instruction covers the moving of data between registers, between memory locations, and between registers and memory locations. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | MOV A, B |
The contents of register B are loaded into register A. |
| 8085 | MOV M, B |
The contents of register B are stored the memory address contained in the
register pair H and L. |
| 8085 | XCHG |
Exchange the contents of the
register pair D and E with the contents of the
register pair H and L. |
This class of instructions cover arithmetic operations such as addition, logical operations such as bitwise OR, and the shift/rotate operations. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | ADD B |
The contents of register B are added to the contents of register A, and
the result is loaded into register A. |
| 8085 | ANA B |
The contents of register B are bitwise ANDed
with the contents of register A, and
the result is loaded into register A. |
| 8085 | SUB M |
The contents of the memory location whose address is contained in the
register pair H and L are
subtracted from the contents of register A, and
the result is loaded into register A. |
| 8085 | RAR |
The contents of register B are rotated right one position and
the result is loaded into register B. |
| 8085 | RLC |
The contents of register A are shifted left one place and
the result is loaded into register A. |
| 8085 | XRA M |
The contents of the memory location whose address is stored in the
register pair H and L are
bitwise exclusive ORed with the contents of register A, and
the result is loaded into register A. |
The control instructions cover conditional jumps, unconditional jumps, and exception/interrupt enabling/disabling.
An unconditional jump can either be a straightforward load of the program counter or a more sophisticated subroutine call and return. Conditional jumping first involves the setting of condition codes (ALU status bits) with a test or compare instruction, then a branch instruction will load the program counter if a certain condition code is set. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | CALL X |
The contents of the program counter are pushed onto the stack then the program counter is loaded with the address X. |
| 8085 | CMP B |
The contents of register B is subtracted from the contents of register A.
No register is loaded with the difference as this instruction is only performed for its effect on the
ALU status bits. |
| 8085 | DI |
Disable interrupts. |
| 8085 | EI |
Enable interrupts. |
| 8085 | JMP X |
The program counter is loaded with the address X. |
| 8085 | JZ X |
The program counter is loaded with the address X if the Z status flag is set.
Otherwise, nothing is done. |
| 8085 | RET |
An address is popped from the stack then the program counter is loaded with this address. |
| 8086 | TEST CX, BX |
The contents of register CX is bitwise ANDed with the contents of register BX.
The result is disregarded as this operation is used only for the generation of ALU status bits.
This instruction is usually followed by a jump if zero, or jump if not zero instruction. |
Sometimes I/O registers are memory mapped so the data movement instructions named above could be used to input and output data. When the I/O registers are not memory mapped but placed on an I/O bus, then instructions will be given for inputting and outputting. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | IN P |
Data found in the 8-bit port P is loaded into register A. |
| 8085 | OUT P |
Data found in register A is stored in the 8-bit port P. |
The addressing mode of an instruction tells us how the instruction's operands are selected. If the operands are in memory then the addressing mode tells us how to calculate an effective address from an operand address. The effective address is the address given to the memory subsystem. The following is a list of the commonly found modes but it is in no way to be considered exhaustive.
In the implied mode the operand is determined solely by the operation. The operands are not explicitly given but are implied by the instruction. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | DAA |
Adjusts the register A to form two 4-bit binary coded decimal digits.
|
| 8086 | PUSHA |
Push the registers AX, CX, DX, BX, SP, BP
DI, and SI onto the stack.
|
In this mode the operand value is included in the instruction itself. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | ADI 3 |
Adds the immediate value 3 to the register A and loads the result back into register A. |
| 8086 | MOV SI, 0 |
Loads the immediate value 0 into the register SI. |
Instructions using the register direct mode have as an operand a register whose contents are used directly. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | ADD B |
Adds the contents of the register B to the register A and loads the result back into register A.
|
| 8086 | MOV AL, BL |
Loads the the register AL with the contents of the register BL.
|
An instruction which employs the register indirect mode uses the contents of a register as an address from which the operand is to be read. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8085 | LDAX B |
Loads the register A with the data at the address contained the the register pair BC.
|
| 8086 | MOV CX, [BX] |
Loads the register CX with the data at the data segment address contained the the register BX.
|
In the register relative addressing mode the instruction contains an offset and the processor calculates the effective address from a register's contents and this offset. Some examples:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8086 | JMP 2 |
Loads the contents of the program counter with the effective address equal to the contents of the current program counter (which addresses
the instruction following the JMP instruction) plus 2 bytes.
In some architectures PC relative effective addressing is considered an addressing mode in its own right.
|
| 8086 | MOV Array[SI], BL |
Stores the contents of register BL
into the data segment effective address
Array plus the contents of register SI.
|
In this mode the operand is stored at an address which is given directly in the instruction. An example:
| Architecture | Instruction | Meaning |
|---|---|---|
| 8086 | MOV AL, Address |
Loads the register AL with the contents of the data segment address Address.
|
This mode is similar to the register indirect mode as the contents of the register contains the address of the operand. However, after being used, the contents of the register is incremented. An example:
| Architecture | Instruction | Meaning |
|---|---|---|
| PDP-11 | MOV (SP)+, X |
Pops the stack and stores the popped value into the memory address X.
Here SP is the stack pointer.
|
This mode is similar to the register indirect mode as the contents of the register contains the address of the operand. However, before being used, the contents of the register is decremented. An example:
| Architecture | Instruction | Meaning |
|---|---|---|
| PDP-11 | MOV X,-(SP) |
Pushes the contents of the memory address X onto the stack.
Here SP is the stack pointer.
|
Exceptions or interrupts are very machine specific. The ISA will have to specify what steps are taken when an exception is signalled and what the programmer needs to do in order to write an exception service routine. Typically a specification will have to include the address of the first instruction to execute when an exception occurs, how exceptions are enabled or disabled, any processor mode changes that are made (user/kernel mode changes), and what machine state is pushed onto the stack upon an exception and what instructions should be executed to pop and restore the machine state off the stack.
Brey, Barry B. The Intel Microprocessors. Sixth Edition. Prentice Hall, 2003.
Elenco. Micro-Master, MM-8000, 8085 Microprocessor - Basic Systems Course. Elenco, 1989.
Hennessy, John L., and Patterson, David A. Computer Architecture a Quantitative Approach. Morgan Kaufman, 1990.
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.
Wulf, William Alan, et al. The Design of an Optimizing Compiler. North Holland, 1975.
Copyright © 2014 Barry Watson. All rights reserved.