An OR gate is a fundamental binary logic gate with N inputs and one output. The output is 1
if any input is 1
.
The equivalent logical connective is disjunction.
The following truth table gives the specification for a two input OR gate with output X
:
A | B | X |
---|---|---|
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 1 |
The schematic form of the OR gate is:
Below is a Verilog structural model for the OR gate.
In the code, the first argument to or
is the gate output, the other arguments are inputs.
module or_gate(X, A, B);
output X;
input A;
input B;
or(X, A, B);
endmodule
Mano, M. Morris, and Kime, Charles R. Logic and Computer Design Fundamentals. 2nd Edition. Prentice Hall, 2000.
Kleitz, W. Digital Microprocessor Fundamentals. 3rd Edition. Prentice Hall, 2000.
Copyright © 2014 Barry Watson. All rights reserved.